Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) has a potential of becoming the “universal” memory combining the non-volatility, fast read/write and high endurance. MRAM chips are made of Magnetic Tunnel Junctions (MTJs), with a typical tri-layer structure: a ferromagnetic free layer which magnetization direction represents the stored memory information, a ferromagnetic pinned layer which magnetization direction is fixed during chip operation to provide spin transfer torque and a tunnel barrier in between that yield different resistivity for parallel or anti-parallel configuration of the magnetization direction of the ferromagnetic free layer and ferromagnetic pinned layer.
FIGS. 1a and 1b are diagrams of a magnetic random access memory cells. In both FIGS. 1a and 1b, an MRAM cell 100 has an MTJ stack 105 connected in series with a gating MOS transistor M1. A first electrode connects the ferromagnetic free layer 110 of the MTJ stack 105 with a bit line 135. The bit line 135 connects the MRAM cell 100 to a bit line decoder (not shown) that provides the necessary voltage and current signals for selecting and operating the MRAM cell 100.
The drain of the gating MOS transistor M1 is connected to a second electrode of the MTJ stack 105. The second electrode is further connected to the ferromagnetic pinned layer 120. The tunnel barrier layer 115 is placed between the ferromagnetic free layer 110 and the ferromagnetic pinned layer 120.
The source of the gating MOS transistor M1 is connected to a source line 145. The source line 145 is connected to the source decoder (not shown) that also provides the necessary voltage and current signals for selecting and operating the MRAM cell 100. The gate of the gating MOS transistor M1 is connected to a word line 140 associated with a column of the MRAM cells 100. The word line 120 is connected to a word line decoder (not shown). The word line decoder supplies a select signal to the gate of the gating MOS transistor M1 to activate or deactivate the gating MOS transistor M1 to select or deselect the MRAM cell 100 for writing or reading.
The ferromagnetic pinned layer 120 has a fixed magnetic spin orientation 125 that is relatively unaffected by the write current through the MTJ stack 105. The ferromagnetic free layer 110 has a selectable magnetic spin orientation 130 that is determined by the direction of the write current through the MTJ stack 105. FIG. 1a shows the parallel state of the MTJ stack 110 where the magnetic orientation of the ferromagnetic free layer 106 and the ferromagnetic pinned layer 108 are parallel or the same direction. This causes the resistance of the MTJ stack 110 to be low or have a commonly accepted digital state of a binary “0”, since electrons preserve their spin orientation during the tunneling process and can only tunnel into the sub-band of the same spin orientation.
FIG. 1b shows the antiparallel state of the MTJ stack 105 where the magnetic orientation of the ferromagnetic free layer 110 and the ferromagnetic pinned layer 120 are in opposite directions or antiparallel. A change from the parallel magnetization configuration in FIG. 1a to the antiparallel configuration (FIG. 1b) of the two electrodes 110 and 120 will result in an exchange between the two spin sub-bands of one of the electrodes 110 and 120 for the tunneling process. The resistance then become relatively high or have a commonly accepted digital state of a binary “1”. It should be noted that the structure for currently fabricated MRAMs have additional layers such as a seed layer, a capping layer and a hard mask layer for performance and integration purposes. The ferromagnetic free layer 110, ferromagnetic pinned layer 120 and the tunnel barrier 115 can have multiple layer structures.
FIG. 2 is a diagram that illustrates multiple MRAM cells 100a, 100b, 100n arranged in a single column of an array of MRAM cells. The MRAM cells 100a, 100b, 100n are structured and function as described above in FIGS. 1a and 1b. The ferromagnetic free layers 110 of the MTJ stacks 105a, 105b, . . . 105n are connected to the bit line 135 and the sources of the gating MOS transistors M1a, M1b, M1n, of the MRAM cells 100a, 100b, 100n are connected to the source line 145. Each of the gates of the gating MOS transistors M1a, M1b, M1n of the MRAM cells 100a, 100b, . . . 100n are connected respectively to the word lines 140a, 140b, . . . 140n. 
The method for reading one of the selected MRAM cells 100a, 100b, 100n is to selectively activate one or more of the gates of the gating MOS transistors M1a, M1b, M1n to turn on the selected gating MOS transistors M1a, M1b, M1n. As described above, an electrical current through the MTJ stacks 105a, 105b, . . . 105n. The voltage developed across the MRAM cells 100a, 100b, 100n is sensed such that the antiparallel high resistance state is interpreted at a binary “1” and the parallel low resistance state is interpreted as a binary “0”.
The method for writing the MRAM cells 100a, 100b, 100n is achieved by passing a larger current selectively through the MTJ stacks 105a, 105b, . . . 105n to change the magnetization direction of the ferromagnetic free layer 110 of the MTJ stacks 105a, 105b, . . . 105n. The ferromagnetic free layer 110 of the selected MTJ stacks 105a, 105b, . . . 105n become spin polarized either passing through or reflected by the ferromagnetic pinned layer 120. Then the spin polarized current will change the ferromagnetic free layer 110 magnetization direction and therefore write the memory cell to the desired binary state. More specifically, an electrical current flowing from the ferromagnetic free layer 110 to the ferromagnetic pinned layer 120 generates a spin transfer torque that aligns the ferromagnetic free layer 110 magnetization direction the same as that of the ferromagnetic pinned layer 120 and writes the memory cell to a binary “0”. When an electrical current is flowing in the opposite direction, from the ferromagnetic pinned layer 110 to the ferromagnetic free layer 110, the electrical current generates a spin transfer torque that aligns the ferromagnetic free layer 110 magnetization direction opposite to that of the ferromagnetic pinned layer 120 and attempts to write the memory cell to a binary “1”. The spin transfer torque is proportional to the amplitude of the electrical current and with an appropriately large current the probability of switching the ferromagnetic free layer 110 magnetization direction is sufficiently large to practically guarantee the switch of the ferromagnetic free layer 110 magnetization and write the selected MRAM cells 100a, 100b, 100n, properly.
Back-hopping is defined as the end result of the switching of the polarization of the ferromagnetic free layer 110 or the ferromagnetic pinned layer 120 is different than the intended. The incorrect switching may be caused by the ferromagnetic pinned layer 120 polarization being flipped or the ferromagnetic free layer 110 being flipped and then being flipped back. The general idea is that if a high voltage is applied after the ferromagnetic free layer 110 switches its polarization to the desired state, there is still strong spin torque on the ferromagnetic pinned layer 120 that tries to switch the magnetization direction of the ferromagnetic pinned layer 120. Then the ferromagnetic pinned layer 120 may switch. Alternately, the ferromagnetic pinned layer 120 may have some magnetization dynamics (i.e. magnetization direction changes with time and is not fixed to either up or down directions) that in turn flips the ferromagnetic free layer 110 back. Either of the two phenomena—the ferromagnetic pinned layer 120 flipping or the ferromagnetic free layer 110 flipping back after an initial switching will result in back-hopping.
The difference between the write currents 150 and 155 of the ferromagnetic free layer 110 and ferromagnetic pinned layer 120 determines the write margin of the selected MRAM cells 100a, 100b, 100n. In an array of MRAM cells, the write current of the ferromagnetic free layer 110 and ferromagnetic pinned layer 120 have stochastic distributions based on process, temperature, operating voltage, operating frequency, etc. Therefore, the design of the minimal write current of ferromagnetic pinned layer 120 must be sufficiently larger than the maximum of the write current of ferromagnetic free layer 110.
The access transistors M1, M2, . . . Mn, can then be turned on and off by activating one word line 140a, 140b, . . . 140n voltage, where one word line 140a, 140b, . . . 140n connects the access transistors on one row. Therefore, an individual MRAM cell can be addressed by selecting one word line 140a, 140b, . . . 140n and one pair of bit lines 135 and source lines 145. Depending on the writing polarity, the electrical current 155 can flow through the bit line 135 to the designated MRAM cells 100a, 100b, . . . 100n, then through the access transistor M1, M2, . . . , Mn and then through the source lines 145. Alternately, the reverse flow will occur and the electrical current 150 will flow through the source lines 145 to the designated MRAM cells 100a, 100b, . . . 100n, then through the access transistor M1, M2, . . . , Mn and then through the bit line 135. The bit lines 135 and source lines 145 in the MRAM device are likely to be placed many metal layers apart and therefore their thickness and resistivity are likely to be different. As a result, the MRAM cells 100a, 100b, . . . 100n on the same column will be in series with a different length of the bit lines 135 and source lines 145, which means that the MRAM cells 100a, 100b, . . . 100n connect to different series resistance for the write process. The actual writing voltage on the MTJ stacks 105a, 105b, . . . 105n at the beginning of the bit line 135 will be different than that of the MTJ stacks 105a, 105b, . . . 105n at the end of the bit line 135. Therefore, the MRAM cell 100n at the end of the bit line 135 does not have enough voltage developed across the MTJ stack 105n for switching and the MRAM cell 100a at the beginning of the bit line 135 already has too much voltage developing across the MTJ stack 105a to cause back hopping in the ferromagnetic pinned layer 120. This effect will become stronger for more advanced technology nodes since the narrower bit lines 135 and source lines 145 in the MRAM device put their resistance closer to that of the MTJ stacks 105a, 105b, . . . 105n and the variation of the bit lines 135 and source lines 145 resistance makes a larger impact for the actual writing voltage on the MTJ stacks 105a, 105b, . . . 105n. 